Regviz

Cypress Semiconductor /psoc63 /EFUSE /SEQ_READ_CTL_3

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SEQ_READ_CTL_3

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Cypress Semiconductor/psoc63/EFUSE/SEQ_READ_CTL_3#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CYCLES0 (STROBE_A)STROBE_A 0 (STROBE_B)STROBE_B 0 (STROBE_C)STROBE_C 0 (STROBE_D)STROBE_D 0 (STROBE_E)STROBE_E 0 (STROBE_F)STROBE_F 0 (STROBE_G)STROBE_G 0 (DONE)DONE

Description

Sequencer read control 3

Fields

CYCLES

Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.
STROBE_A

Specifies value of eFUSE control signal strobe_f
STROBE_B

Specifies value of eFUSEcontrol signal strobe_b
STROBE_C

Specifies value of eFUSE control signal strobe_c
STROBE_D

Specifies value of eFUSE control signal strobe_d
STROBE_E

Specifies value of eFUSE control signal strobe_e
STROBE_F

Specifies value of eFUSE control signal strobe_f
STROBE_G

Specifies value of eFUSE control signal strobe_g
DONE

When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.

Links

()

Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data